我发一个Verilog和计数器和波形和大家一起分享。 计数器, 波形, Verilog, 分享

latin

module d_chu(over,out,clk,enable);
input clk,enable;
output [1:8]out;
output over;
reg  [1:8]out;
reg  over;
initial  
begin
out='d0;
over=1;
end
always
@(posedge clk) begin

if(over)
over=0;
if (enable)
out=out+1;
if(out=='b11111111)
begin
out='d0;
over=1;
end
end
endmodule


module  d_chu_test;
reg  enable1,clk1,clr1;
wire [1:8]out1;
wire over1;
d_chu q (over1,out1,clk1,enable1);


always
begin
#20 clk1=0;
#20 clk1=1;  
end

always
begin
#600 enable1=1;
// #600 enable1=0;
end


endmodule   
   

[em27][em26]

leonyang

热情可佳，但是这个也要发？疑惑中