| 典型的总线操作
按照
input cpu_wren , cpu_rden;
input cpu_clk;
inout [7:0] cpu_data;
input [15:0] cpu_addr;
always@(posedge clk or posedge reset)
begin
if(reset)
wrdata <= 0;
else
if(cpu_wren &(cpu_addr = wraddr))
wrdata <= cpu_data;
end
assign cpu_data = (cpu_rden) ? rddata : 8'haa;
endmodule
注意读写使能的长度可能根据时序要调整一下 |
