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- UID
- 96445
- 性别
- 男
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| 语法检查的时候告诉有错误，帮忙改一下，在此感谢拉
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity count_top is
Port ( CLKIN : in std_logic;
RST : in std_logic;
CE : in std_logic;
LD : in std_logic;
UP : in std_logic;
DI : in std_logic_vector(15 downto 0);
DOUT : out std_logic_vector(15 downto 0));
end count_top;
architecture Behavioral of count_top is
component counter
port ( CLK: in STD_LOGIC;
RESET: in STD_LOGIC;
CE, LOAD, DIR: in STD_LOGIC;
DIN: in STD_LOGIC_VECTOR(15 downto 0);
COUNT: inout STD_LOGIC_VECTOR(15 downto 0));
end component;
signal N:std_logic_vector(20 downto 0);
begin
counter_part:counter port map(
CLKIN(N(20))=>CLK,
RST=>RESET,
CE=>CE,
LD=>LOAD,
UP=>DIR,
DI=>DIN,
DOUT=>COUNT);
process(CLKIN)
begin
if(CLKIN'event and CLKIN='1') then
N<=N+1;
end if;
end process;
CLK<=N(20);
end Behavioral; |
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