用的芯片是altera的EP1K30TC144-3
作一个能显示时．分．秒的数字钟
有人用verilog编了一个程序
结果出来的device是max７０００系列的
不能用
我又不会改
大家给看看吧
module Dclock(clkin, //时钟输入1M
hour, //时输出
minute, //分输出
second, //秒输出
hourup, //时增加
hourdown, //时减少
minuteup, //分增加
minutedown, //分减少
alarm); //闹钟
input clkin,hourup,hourdown,minuteup,minutedown;
output alarm;
output [5:0] hour,minute,second;
reg [5:0] hour,minute,second;
reg [19:0] clkcounter;
reg sclk;
reg mclk;
reg hclk;
reg alarm;
initial
begin
hour=0;
minute=0;
second=0;
clkcounter=0;
sclk=0;
mclk=0;
hclk=0;
alarm=0;
end
////输入1M的时钟产生周期1s的时钟信号
always @(posedge clkin)
begin
if(clkcounter==100)
begin
clkcounter<=0;
sclk<=1;
end
else
begin
clkcounter<=clkcounter+1;
sclk<=0;
end
end
//////秒计数///////////////
always @(posedge sclk)
begin
if(second==60)
begin
second<=0;
mclk<=1;
end
else
begin
second<=second+1;
mclk<=0;
end
end
////分计数//////////
always @(posedge mclk/* or posedge minuteup or posedge minutedown*/)
begin
if(minute==60)
begin
hclk<=1;
minute<=0;
end
else
begin
hclk<=0;
minute<=minute+1;
end
end
//////时计数/////////////////
always @(posedge hclk/* or posedge hourup or posedge hourdown*/)
begin
if(hour==24)
begin
hour<=0;
end
else
begin
hour<=hour+1;
end
end
////闹钟/////////////////////
always @(posedge clkin)
begin
if(minuteup==0) begin
if(minutedown==0) begin
if(hourup==0) begin
if(hourdown==0) begin
case(minute)
55:begin
if(clkcounter<50) alarm<=1;
else alarm<=0;
end
56:begin
if(clkcounter<50) alarm<=1;
else alarm<=0;
end
57:begin
if(clkcounter<50) alarm<=1;
else alarm<=0;
end
58:begin
if(clkcounter<50) alarm<=1;
else alarm<=0;
end
59:begin
if(clkcounter<50) alarm<=1;
else alarm<=0;
end
60:alarm<=1;
default:alarm<=0;
endcase
end
end
end
end
end
endmodule
