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- UID
- 92799
- 性别
- 男
|
| Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package coeffs is
type coef_arr is array (0 to 16) of signed (8 downto 0);
constant coefs: coef_arr:=(
"000000001", "000000001", "000000000", "000000001",
"111111111", "111111110", "000000011", "000000010",
"111111110", "000000010", "000000000", "111111110",
"111111111", "000000001", "000000001", "111111110",
"111111101");
end coeffs;
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.coeffs.all;
entity fir is
port(clk,reset: in std_logic;
sample: in signed (7 downto 0);
result: out signed ( 16 downto 0));
end fir;
architecture beh of fir is
begin
process
type shift_arr is array (16 downto 0) of signed (7 downto 0);
variable tmp,old:signed(7 downto 0);
variable pro:signed (16 downto 0);
variable acc:signed (16 downto 0);
variable shift:shift_arr;
begin
for i in sample'range loop --zero out the shift register
tmp:=sample;
shift(i):=(others=>'0');
end loop;
result<=(others=>'0');
acc:=(others=>'0');
for i in sample'range loop
WAIT UNTIL clk'EVENT AND clk = '1';
shift(0):=tmp;
old:=shift(i);
pro:=shift(0)*coefs(i);
acc:=acc+pro;
shift(i+1):=shift(i);
end loop;
result<=acc;
end process;
end beh;
Error: VHDL Process Statement error at Fir.vhd(27): Process Statement must contain only one Wait Statement
Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings
Error: Processing ended: Fri Jan 14 09:32:31 2005
Error: Elapsed time: 00:00:00
Error: Quartus II Full Compilation was unsuccessful. 1 error, 0 warnings
请各位大侠指点！！ |
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