[求助]Protel PLD设计问题？？ PLD, Protel, 求助, 设计

xqbuiang

我用Atmel公司的ATV750b设计一个8位同步计数器！我是在Protel中画的原理图，编译时老提示这样的错误： Advanced PLD99 Netlist Translator Started on 2004-3-4 at 16:39:56 Schematic Translator successful. Output file, E:\Design Explorer 99 SE\Examples\My PLD\PldDesign1.pld has been created. Advanced PLD99 Compiler Started on 2004-3-4 at 16:39:57 CUPLX time: 0 secs CUPLA time: 0 secs CUPLB [0012cb] pin/node 0 Invalid usage: NetU1_I time: 0 secs Total time: 0 secs Fatal CUPL errors encountered ... program aborted! 虚拟编译可以通过。是不是加入脉冲的地方出错拉？？望高手指点！谢谢！