大家好，这是我编的测试模块，但总有很多错误，不知道为什么，请大伙给我看看，谢谢了！ `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:39:09 09/16/2008
// Design Name: sdb_check
// Module Name: sdb_check_tbw.v
// Project Name: ad9430
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: sdb_check
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////// module sdb_check_tbw_v; // Inputs
reg RST;
reg CLK;
reg [15:0] DATAIN;
reg WEN; // Outputs
wire DELAY;
wire TRANS_HOLD;
wire TRANS_START;
wire CALEND;
wire FULL;
wire INPUT_ERRORS;
wire PAUSE;
wire [15:0] DATAOUT;
wire [3:0] CASES;
wire ERROR;
reg[15:0] data[20:0];
reg[15:0] data[0]=16'b1010101001010101,//THE judgement of the head of frame;
data[1]=16'b1010101001010101,
data[2]=16'b0101010101010000, //change to the case check of the frame;
data[3]=16'b0101010101010000,
data[4]=16'b0101010101011001, //go to the case of trans_start;
data[5]=16'b0101010101011010, // GO TO THE CASE OF TRANS_HOLD;
data[6]=16'b0101010101011011, //GO TO THE CASE OF DELAY;
data[7]=16'b0101010101011100, //GO TO THE CASE OF CALEND;
data[8]=16'b0101010101011101, //GO TO THE CASE OF ERROR;
data[9]=16'b0101010101010111, //GO TO THE CASE OF FULL;
data[10]=16'b0101010101010101, //GO TO THE CASE OF PAUSE;
data[11]=16'b0101010101010101,
data[12]=16'b1010101001011101;//这种情况是不存在的，错误的;
reg[15:0] data[13]=16'b1010101001010101,
data[14]=16'b0101010101010000,
data[15]=16'b0101010101011001,
data[16]=16'b0101010101011010,
data[17]=16'b0101010101011011,
data[18]=16'b0101010101011100,
data[19]=16'b0101010101011111, //错误状态
data[20]=16'b1010101001010101; // Instantiate the Unit Under Test (UUT)
sdb_check uut (
.RST(RST),
.CLK(CLK),
.DATAIN(DATAIN),
.WEN(WEN),
.DELAY(DELAY),
.TRANS_HOLD(TRANS_HOLD),
.TRANS_START(TRANS_START),
.CALEND(CALEND),
.FULL(FULL),
.INPUT_ERRORS(INPUT_ERRORS),
.PAUSE(PAUSE),
.DATAOUT(DATAOUT),
.CASES(CASES),
.ERROR(ERROR)
); initial begin
// Initialize Inputs
RST = 0;
CLK = 0;
DATAIN = 0;
WEN = 0; // Wait 100 ns for global reset to finish
#100;
RST = 1;
#100;
RST = 0;
// Add stimulus here end
always@(posedge CLK)
if(!RST)
begin
for(i=0;i=20;i=i+1)
DATAIN=data;
end
always #500 WEN=~WEN;
always #1000 RST=~RST;
always #4 CLK=~ CLK;
endmodule
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