LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE WORK.my_pkg.ALL; ENTITY clkgen IS
PORT(sysres,en1,clk:IN STD_ULOGIC;
cntclk,keyclk:OUT STD_ULOGIC);
END clkgen; ARCHITECTURE rtl OF clkgen IS
COMPONENT cnt10
PORT(reset,en,clk:IN STD_ULOGIC;
carry:OUT STD_ULOGIC;
q:OUT STD_ULOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT ;
COMPONENT cnt4
PORT(reset,en,clk:IN STD_ULOGIC;
carry:OUT STD_ULOGIC;
q:OUT STD_ULOGIC_VECTOR(1 DOWNTO 0));
END COMPONENT; SIGNAL cntclk_S:STD_ULOGIC;
BEGIN
u0:cnt10 PORT MAP(sysres,en1,clk,cntclk_s);
u1:cnt4 PORT MAP(sysres,cntclk_s,clk,keyclk);
cntclk<=cntclk_s;
END rtl; 红色处报错：Unsupported feature error:Enumeration Type Definition not supported in Port Declaration of the Component Instantion Statement 请大侠们指点下，感激不尽 | 
