增减计数器 增减, 计数器

sailms

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity count is
port(clk,dir,rst:in std_logic;
count:buffer std_logic_vector(3 downto 0));
end count;

architecture Behavioral of count is

begin
process(clk,dir,rst)
begin
if(rst='1')then
count<="0001";
else
if(clk'event and clk='1')then
if(dir='1')then
count<=count+1;
else
count<=count-1;
end if;
end if;
end if;
end process;
end Behavioral;

请问为什么以上代码可以综合，但是无法仿真呢？？？

ERROR:HDLParsers:1202 - "E:/kao2/gfdh.vhw" Line 43. Redeclaration of symbol count.
ERROR:HDLParsers:402 - "E:/kao2/gfdh.vhw" Line 58. Component 'count' count can not be used as a primary name.
Parsing "gfdh_beh.prj": 0.11
ERROR: Fuse failed

以上是仿真时的报错

[em66][em66][em66][em66][em66][em66][em66][em66][em66][em107][em107][em107][em107]

sailms

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 7.1i
-- \ \ Application : ISE Foundation
-- / / Filename : gfdh.vhw
-- /___/ /\ Timestamp : Wed Nov 05 23:32:54 2008
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name: gfdh
--Device: Xilinx
--

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY gfdh IS
END gfdh;

ARCHITECTURE testbench_arch OF gfdh IS
COMPONENT count
PORT (
clk : In std_logic;
dir : In std_logic;
rst : In std_logic;
count : Buffer std_logic_vector (3 DownTo 0)
);
END COMPONENT;

SIGNAL clk : std_logic := '0';
SIGNAL dir : std_logic := '0';
SIGNAL rst : std_logic := '1';
SIGNAL count : std_logic_vector (3 DownTo 0) := "0000";

SHARED VARIABLE TX_ERROR : INTEGER := 0;
SHARED VARIABLE TX_OUT : LINE;

constant PERIOD : time := 200 ns;
constant DUTY_CYCLE : real := 0.5;
constant OFFSET : time := 0 ns;

BEGIN
UUT : count
PORT MAP (
clk => clk,
dir => dir,
rst => rst,
count => count
);

PROCESS -- clock process for clk
BEGIN
WAIT for OFFSET;
CLOCK_LOOP : LOOP
clk <= '0';
WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE));
clk <= '1';
WAIT FOR (PERIOD * DUTY_CYCLE);
END LOOP CLOCK_LOOP;
END PROCESS;

PROCESS
BEGIN
-- ------------- Current Time: 1085ns
WAIT FOR 1085 ns;
dir <= '1';
rst <= '0';
-- -------------------------------------
-- ------------- Current Time: 4085ns
WAIT FOR 3000 ns;
dir <= '0';
-- -------------------------------------
-- ------------- Current Time: 6885ns
WAIT FOR 2800 ns;
dir <= '1';
-- -------------------------------------
-- ------------- Current Time: 9085ns
WAIT FOR 2200 ns;
rst <= '1';
-- -------------------------------------
WAIT FOR 1115 ns;

IF (TX_ERROR = 0) THEN
STD.TEXTIO.write(TX_OUT, string'("No errors or warnings"));
ASSERT (FALSE) REPORT
"Simulation successful (not a failure). No problems detected."
SEVERITY FAILURE;
ELSE
STD.TEXTIO.write(TX_OUT, TX_ERROR);
STD.TEXTIO.write(TX_OUT,
string'(" errors found in simulation"));
ASSERT (FALSE) REPORT "Errors found during simulation"
SEVERITY FAILURE;
END IF;
END PROCESS;

END testbench_arch;

补上

[em72][em72][em72]

sailms

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY gfdh IS
END gfdh;

ARCHITECTURE testbench_arch OF gfdh IS
COMPONENT count
PORT (
clk : In std_logic;
dir : In std_logic;
rst : In std_logic;
count : Buffer std_logic_vector (3 DownTo 0)
);
END COMPONENT;

SIGNAL clk : std_logic := '0';
SIGNAL dir : std_logic := '0';
SIGNAL rst : std_logic := '1';
SIGNAL count : std_logic_vector (3 DownTo 0) := "0000";

SHARED VARIABLE TX_ERROR : INTEGER := 0;
SHARED VARIABLE TX_OUT : LINE;

constant PERIOD : time := 200 ns;
constant DUTY_CYCLE : real := 0.5;
constant OFFSET : time := 0 ns;

BEGIN
UUT : count
PORT MAP (
clk => clk,
dir => dir,
rst => rst,
count => count
);

PROCESS -- clock process for clk
BEGIN
WAIT for OFFSET;
CLOCK_LOOP : LOOP
clk <= '0';
WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE));
clk <= '1';
WAIT FOR (PERIOD * DUTY_CYCLE);
END LOOP CLOCK_LOOP;
END PROCESS;

PROCESS
BEGIN
-- ------------- Current Time: 1085ns
WAIT FOR 1085 ns;
dir <= '1';
rst <= '0';
-- -------------------------------------
-- ------------- Current Time: 4085ns
WAIT FOR 3000 ns;
dir <= '0';
-- -------------------------------------
-- ------------- Current Time: 6885ns
WAIT FOR 2800 ns;
dir <= '1';
-- -------------------------------------
-- ------------- Current Time: 9085ns
WAIT FOR 2200 ns;
rst <= '1';
-- -------------------------------------
WAIT FOR 1115 ns;

IF (TX_ERROR = 0) THEN
STD.TEXTIO.write(TX_OUT, string'("No errors or warnings"));
ASSERT (FALSE) REPORT
"Simulation successful (not a failure). No problems detected."
SEVERITY FAILURE;
ELSE
STD.TEXTIO.write(TX_OUT, TX_ERROR);
STD.TEXTIO.write(TX_OUT,
string'(" errors found in simulation"));
ASSERT (FALSE) REPORT "Errors found during simulation"
SEVERITY FAILURE;
END IF;
END PROCESS;

END testbench_arch;

不好意思，上面那个，不完全

[em72]

sailms

呃……没办法一次发完…………

[em61][em61][em61][em61]

sailms

我是新手，刚刚没弄清楚，原来重新进入就可以看到全部内容了，请各位就看最上面的两份帖子[em72][em72][em72][em72][em72][em72]

sailms

解决了是也