VHDL编程求救啊~~各位大哥大姐帮忙啊 VHDL, 大姐, 求救, 帮忙

VHDL

opcode: in std_logic_vector(2 downto 0);
A,B: in std_logic_vector(3 downto 0);
output: out std_logic_vector(3 downto 0);
zero: out std_logic);
要求是
opcode operation description
001 compare zero<=1,when A=B
010 Multiply by 2 output<=BX2
011 Divide by 2 output<=A/2
100 and output<=A and B
101 nor output<=A nor B
110 or output<=A or B
111 Xor output<=A xor B
有没有高手能帮我解决阿 这是我VHDL这学期考试的最后一道题目阿
要有代码和最后画出来的波形图.
可以发我的邮箱:zmhgoodboy@hotmail.com
谢谢!!谢谢!!!

VHDL

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity FinalProject is

port(opcode: in bit_vector(2 downto 0);

A,B: in bit_vector(3 downto 0);

output1: out bit_vector(3 downto 0);

zero: out bit_vector);

end FinalProject;

architecture behavioral of FinalProject is

begin

process (A,B)

begin

if A=B then

zero<="1";

else

Case opcode is

when"001"=>zero<="1";

when "010" => output1 <= (B*B);

when "011" =>output1<= (A/2);

when "100" => output1 <= (A and B);

when "101" => output1 <= (A nor B);

when "110" => output1<= (A or B);

when "111" => output1<= (A xor B);

when others => output1 <= "0000";

end case;

end if;

end process ;

end Behavioral;

这个是我看了资料编的 但是在乘法和除法上还是不行 有没有大哥能指点我一下的啊 十万火急 真的希望有好心人能帮帮我啊

VHDL

哪位大哥有空帮我看一下我的代码 谢谢了