我今天直接调了个DDR2控制器IP核作为顶层，综合能过，加上DQ和DQS管脚约束，fitter时就报
Error: The I/O standard LVDS cannot be used on the Bidir pin mem_clk[0].双向信号不能用差分。
（使用stx3，直接用IP核作为顶层综合，未修改任何内容，只加了DQ和DQS管脚约束）
DDR2 IP核用户手册又说：
The "mem_clk" signals are output only signals from the FPGA. However,
in the Quartus II software they must be defined as bidirectional (INOUT) I/Os to support
the mimic path structure that the altmemphy megafunction uses. 请各位多多指点 | 
