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-- Company:
-- Engineer:
--
-- Create Date: 11:17:12 04/13/2009
-- Design Name: DDFS
-- Module Name: D:/vhdl/dds1/out_txt.vhd
-- Project Name: dds1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: DDFS
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
library STD;
use STD.TEXTIO.ALL; ENTITY out_txt_vhd IS
END out_txt_vhd; ARCHITECTURE behavior OF out_txt_vhd IS -- Component Declaration for the Unit Under Test (UUT)
COMPONENT DDFS
PORT(
CLK : IN std_logic;
reset : IN std_logic;
Freq_Data : IN std_logic_vector(13 downto 0);
Dout : OUT std_logic_vector(14 downto 0);
Dac_clk : OUT std_logic
);
END COMPONENT; --Inputs
SIGNAL CLK : std_logic := '0';
SIGNAL reset : std_logic := '0';
SIGNAL Freq_Data : std_logic_vector(13 downto 0) := "00011110101110";--(others=>'0');
-- 32109876543210
--Outputs
SIGNAL DDS_Out : std_logic_vector(14 downto 0);
SIGNAL Dac_clk : std_logic;
file out_file:text is out "d:\out_file.txt"; BEGIN -- Instantiate the Unit Under Test (UUT)
uut: DDFS PORT MAP(
CLK => CLK,
reset => reset,
Freq_Data => Freq_Data,
Dout => DDS_Out,
Dac_clk => Dac_clk
);
clk<=not clk after 0.5ns; --100Mhz
tb : PROCESS
BEGIN
reset<='0';
wait for 0.1 ns; -- Wait 20 ns for global reset to finish
reset<='1';
-- Place stimulus here wait; -- will wait forever
END PROCESS;
PROCESS(DDS_Out)
variable out_line:line;
begin
write(out_line,to_bitvector(DDS_Out));
writeline(out_file,out_line);
end process; END;
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