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FPGA/CPLD可编程逻辑

[ 26527 主题 / 25683 回复 ]

版块介绍: 讨论关于FPGA和CPLD的相关话题!

版主: boyfly, stone133, flanix, bydxdtcdj, 电子狂热, xcx_hust, benbenfei, AndyLee008

FPGA/CPLD可编程逻辑

    标题 作者 回复/查看 最后发表
common   FPGA查找表 look_w 2017-11-16 0/371 look_w 2017-11-16 12:52
common   如何采用FPGA协处理器实现算法加速 look_w 2017-11-16 0/791 look_w 2017-11-16 12:51
common   异步FIFO在系统中的使用 look_w 2017-11-16 0/402 look_w 2017-11-16 12:48
common   用Quartus II + Verilog 做FPGA/CPLD设计/仿真的几个基本问题 look_w 2017-11-16 0/545 look_w 2017-11-16 12:47
common   用Quartus II + Verilog 做FPGA/CPLD设计/仿真的几个基本问题 look_w 2017-11-16 0/902 look_w 2017-11-16 12:46
common   Verilog编写的Uart程序 look_w 2017-11-16 0/598 look_w 2017-11-16 12:42
common   使用Quartus II进行CPLD仿真 look_w 2017-11-16 0/378 look_w 2017-11-16 12:41
common   CPU通过SMC控制CPLD look_w 2017-11-16 0/351 look_w 2017-11-16 12:38
common   Altera CPLD学习笔记 look_w 2017-11-16 0/367 look_w 2017-11-16 12:35
common   Lattice USB下载线使用说明及CPLD程序烧写 look_w 2017-11-16 0/734 look_w 2017-11-16 12:34
common   基于STM32和CPLD可编程逻辑器件的等精度测频技术 look_w 2017-11-16 0/372 look_w 2017-11-16 12:31
common   采用CPLD或者FPGA显示TFT液晶屏 look_w 2017-11-16 0/933 look_w 2017-11-16 12:29
common   建立保持时间(CPLD时序分析) look_w 2017-11-16 0/835 look_w 2017-11-16 12:27
common   时钟分频引起的问题 look_w 2017-11-16 0/561 look_w 2017-11-16 12:24
common   测试在不同的地方对同一信号赋值 look_w 2017-11-16 0/392 look_w 2017-11-16 12:23
common   开关量检测 look_w 2017-11-16 0/550 look_w 2017-11-16 12:22
common   TimeQuest API: 时钟约束 look_w 2017-11-16 0/581 look_w 2017-11-16 12:21
common   FPGA中竞争冒险问题的研究(2) look_w 2017-11-16 0/605 look_w 2017-11-16 12:20
common   FPGA中竞争冒险问题的研究(1) look_w 2017-11-16 0/446 look_w 2017-11-16 12:19
common   FPGA的SoC设计方法 look_w 2017-11-16 0/572 look_w 2017-11-16 12:16
common   什么是CPLD look_w 2017-11-16 0/335 look_w 2017-11-16 12:15
common   Verilog中 reg和wire 用法和区别以及always和assign的区别 look_w 2017-11-16 0/321 look_w 2017-11-16 12:13
common   ARM+FPGA如何入门,如何学习入门嵌入式 look_w 2017-11-16 0/383 look_w 2017-11-16 12:11
common   FPGA和CPLD对比与入门 look_w 2017-11-16 0/336 look_w 2017-11-16 12:10
common   FPGA和CPLD的区别 look_w 2017-11-16 0/361 look_w 2017-11-16 12:08
common   FPGA之学习FPGA需要注意的地方 look_w 2017-11-7 0/446 look_w 2017-11-7 16:57
common   FPGA之ZedBoard入门 look_w 2017-11-7 0/418 look_w 2017-11-7 16:56
common   FPGA开发之Tcl的基于项目设计 look_w 2017-11-7 0/464 look_w 2017-11-7 16:54
common   FPGA开发之eCos系统 look_w 2017-11-7 0/426 look_w 2017-11-7 16:52
common   FPGA开发之问题二 look_w 2017-11-7 0/449 look_w 2017-11-7 16:50
common   FPGA开发之问题一 look_w 2017-11-7 0/428 look_w 2017-11-7 16:48
common   FPGA开发之控制集control sets look_w 2017-11-7 0/392 look_w 2017-11-7 16:47
common   FPGA之新套件Vivado的新性能 look_w 2017-11-7 0/428 look_w 2017-11-7 16:47
common   FPGA开发之时钟管理模块 look_w 2017-11-7 0/327 look_w 2017-11-7 16:46
common   FPGA开发之时序约束(周期约束) look_w 2017-11-7 0/429 look_w 2017-11-7 16:44
common   FPGA开发之引脚和区域约束语法 look_w 2017-11-7 0/412 look_w 2017-11-7 16:43
common   FPGA开发之planahead look_w 2017-11-7 0/411 look_w 2017-11-7 16:42
common   FPGA开发流程1(详述每一环节的物理含义和实现目标F) look_w 2017-11-4 0/349 look_w 2017-11-4 13:42
common   FPGA开发流程1(详述每一环节的物理含义和实现目标E) look_w 2017-11-4 0/582 look_w 2017-11-4 13:40
common   FPGA开发流程1(详述每一环节的物理含义和实现目标D) look_w 2017-11-4 0/403 look_w 2017-11-4 13:39
    类型 排序方式 时间范围