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FPGA/CPLD可编程逻辑

[ 26527 主题 / 25683 回复 ]

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版块介绍: 讨论关于FPGA和CPLD的相关话题！

版主: boyfly, stone133, flanix, bydxdtcdj, 电子狂热, xcx_hust, benbenfei, AndyLee008

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FPGA/CPLD可编程逻辑

    标题 作者 回复/查看 最后发表
common   FPGA引脚直接接6.25V yuchengze 2016-11-24 0/351 yuchengze 2016-11-24 21:57
common   请教SPARTAN-3E的一个问题 yuchengze 2016-11-24 0/460 yuchengze 2016-11-24 21:56
common   基于verilog的数字密码锁 yuchengze 2016-11-24 0/428 yuchengze 2016-11-24 21:54
common   关于FPGA特殊引脚CRC_ERROR 在QII中如何设置为普通IO口？ yuchengze 2016-11-24 0/477 yuchengze 2016-11-24 21:53
common   【求助】：在ISE10.1功能仿真时正确，时序仿真结果出错 [ yuchengze 2016-11-24 0/530 yuchengze 2016-11-24 21:49
common   FPGA 下载问题 yuchengze 2016-11-24 0/362 yuchengze 2016-11-24 21:47
common   做PS2发现的奇怪问题，求解答 yuchengze 2016-11-24 0/423 yuchengze 2016-11-24 21:45
common   请教关于SPARTAN-3E的问题 yuchengze 2016-11-24 0/583 yuchengze 2016-11-24 21:43
common   有人用actel的fpga吗？ yuchengze 2016-11-24 0/489 yuchengze 2016-11-24 21:42
common   帮我看看这个程序哪有错？ yuchengze 2016-11-24 0/360 yuchengze 2016-11-24 21:40
common   在7x24小时的应用中，是否需要考虑FPGA软错误？ yuchengze 2016-11-24 0/588 yuchengze 2016-11-24 21:38
common   altrea I/O配置 yuchengze 2016-11-24 0/387 yuchengze 2016-11-24 21:37
common   请教多块芯片同时烧写的问题 yuchengze 2016-11-24 0/503 yuchengze 2016-11-24 21:36
common   一个关于verilog的程序,请教下!! yuchengze 2016-11-24 0/457 yuchengze 2016-11-24 21:33
common   连载4－《锁相环技术原理及FPGA实现》－前言 yuchengze 2016-11-24 0/519 yuchengze 2016-11-24 21:32
common   两种写法，感觉应该更稳定，却出现了问题 yuchengze 2016-11-24 0/386 yuchengze 2016-11-24 21:29
common   Xilinx FPGA入门31：超声波测距回响脉宽计数之均值滤波处理 yuchengze 2016-11-24 0/343 yuchengze 2016-11-24 21:28
common   连载5－《锁相环技术原理及FPGA实现》－4.1. yuchengze 2016-11-24 0/486 yuchengze 2016-11-24 21:25
common   vivado 设置上电加载速度 yuchengze 2016-11-24 0/566 yuchengze 2016-11-24 21:24
common   FPGA开发板xilinx spartan-6 xc6slx100T yuchengze 2016-11-24 0/449 yuchengze 2016-11-24 21:23
common   代码编译正确，但是不能按照设计显示，求大神指教 yuchengze 2016-11-24 0/476 yuchengze 2016-11-24 21:22
common   Xilinx FPGA入门35：超声波测距终极结果显示之乘法器IP解析 yuchengze 2016-11-24 0/460 yuchengze 2016-11-24 21:21
common   lattice菜鸟求助 yuchengze 2016-11-24 0/704 yuchengze 2016-11-24 21:19
common   FPGA配置文件的问题 yuchengze 2016-11-24 0/467 yuchengze 2016-11-24 21:16
common   Cyclone V Soc型号 yuchengze 2016-11-24 0/447 yuchengze 2016-11-24 21:15
common   关于FPGA连续写入FIFO后NiosII读取数据错误的问题 yuchengze 2016-11-24 0/375 yuchengze 2016-11-24 21:14
common   Xilinx FPGA入门连载37：SRAM读写测试之时序解读 yuchengze 2016-11-24 0/448 yuchengze 2016-11-24 21:12
common   有人用FPGA做过视频图像的自动白平衡算法没？求交流 yuchengze 2016-11-24 0/492 yuchengze 2016-11-24 21:11
common   感谢kaiseradler，帮我解决了spartan6的配置问题，与诸位分享 yuchengze 2016-11-24 0/787 yuchengze 2016-11-24 21:10
common   关于两块FPGA板之间做简单同步出现的问题 yuchengze 2016-11-24 0/599 yuchengze 2016-11-24 21:10
common   安装xilinx ISE 12.4软件 yuchengze 2016-11-24 0/605 yuchengze 2016-11-24 21:08
common   Xilinx FPGA入门连载48：FPGA片内RAM实例之RAM配置 yuchengze 2016-11-24 0/497 yuchengze 2016-11-24 21:06
common   FPGA视频课程-第三章 入门基础 yuchengze 2016-11-24 0/464 yuchengze 2016-11-24 21:05
common   NIOS软核美国根本没人用，都是厂家忽悠，还是别学了 yuchengze 2016-11-24 0/830 yuchengze 2016-11-24 21:04
common   FPGA开发板 yuchengze 2016-11-24 0/422 yuchengze 2016-11-24 21:03
common   ISE MAP时间长，请大家帮忙看看！ yuchengze 2016-11-24 0/419 yuchengze 2016-11-24 21:02
common   FPGA实战演练逻辑篇67：测试脚本编写 yuchengze 2016-11-24 0/436 yuchengze 2016-11-24 21:00
common   ISE PhysDesignRules yuchengze 2016-11-24 0/487 yuchengze 2016-11-24 21:00
common   怎么约束逻辑在bank里面，求刺！ yuchengze 2016-11-24 0/321 yuchengze 2016-11-24 20:59
common   Xilinx FPGA入门连载50：FPGA片内RAM实例之chipscope在线调试 [ yuchengze 2016-11-24 0/510 yuchengze 2016-11-24 20:58
    类型 排序方式 时间范围    
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