vhdl的小程序编译通过,可在SYNTHESIS却有这个毛病! SYNTHESIS, vhdl, 毛病, 程序, 编译

yufeng0810

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FPGA IS
     PORT (          PCLK:IN STD_LOGIC;
                       VSYNC:IN STD_LOGIC;
                       HREF  :IN STD_LOGIC;
                                D:IN STD_LOGIC_VECTOR(9 DOWNTO 0);
                                Y:OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
                 );
END FPGA;
ARCHITECTURE GET_DATA OF FPGA IS
     BEGIN
          PROCESS(VSYNC)
                VARIABLE Q :INTEGER RANGE 0 TO 12396;      
          BEGIN
          IF(VSYNC'EVENT AND VSYNC='0')THEN
              IF(PCLK'EVENT AND PCLK='1')THEN
                    IF  (Q = 12396)THEN
                         IF (HREF'EVENT AND HREF='1')THEN
                             Y<=D;
                             Q:= 0;
                          END IF;                              
                     ELSE Q:=Q+1;    
                     END IF;
                END IF;
          END IF; 
          END PROCESS;
END GET_DATA;    

 

 

THIS USE OF CLOCK EDGE SPECIFICATION NOT SUPORT IN RUTION FPGA LINE 17 IN FILE,请求帮助!谢谢