请问下面的代码编译以后，为什么addr地址线总是连不上？？？？
library IEEE;
use IEEE.std_logic_1164.all;
package instr is
type instruction is (add, sub, lda, ldb, sta, stb, outa, xfr);
end instr;
use work.instr.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity mp is
port(instr : in instruction;
addr : in integer;
data : inout integer
);
end mp;
architecture mp of mp is
begin
process(instr, addr)
type regtype is array(0 to 255) of integer;
variable a, b : integer;
variable reg : regtype;
begin
case instr is --select instr to execute
when lda =>
a := data; --load a accumulator
when ldb =>
b := data; --load b accumulator
when add =>
a := a + b;
when sub =>
a := a - b;
when sta =>
reg(addr) := a; --put a accum into reg array
when stb =>
reg(addr) := b; -- put b accum in to reg array
when outa =>
data <= a; --output a accum
when xfr => --transfer b to a
a := b;
end case;
end process;
end mp;
| 
ut std_logic);