底下这段程序在综合时出现这样的情况:No matching overload for "+"?"+"(signal:count, 1)
这是什么原因呢?
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_arith_1164.all;
--use ieee.std_unsigned_1164.all;
entity clk_div is
port(clk: in std_logic;
clk_6div: out std_logic
);
end clk_div;
architecture rtl of clk_div is
signal count:std_logic_vector(2 downto 0);
constant md:std_logic_vector(2 downto 0):="101";
begin
process(clk)
begin
if(clk'event and clk='1')
then
if (count=md) then
count<=(others=>'0');
else
count<=count+1;
end if;
end if;
end process;
process(clk)
begin
if(clk'event and clk='1') then
if (count=md) then
clk_6div<='1';
else
clk_6div <='0';
end if;
end if;
end process ;
end rtl;
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