基于FPGA的流水线设计（2） always, 流水线

yuyang911220

module liu_2(clk,rst,dout_1,en_1,en_2,dout_2);
input clk;
input rst;
input[31:0] dout_1;
input en_1;
output en_2;
output[15:0] dout_2;

reg[15:0] dout_2;
reg en_2;

always@(posedge clk)
begin
if(!rst) begin dout_2 <= 16'h0000;en_2 <= 0; end
else if(en_1) begin dout_2 <= dout_1[31:16];en_2 <= 1; end
else en_2 <= 0;
end

endmodule


module liu_3(clk,rst,dout_2,en_2,en_3,dout_3);
input clk;
input rst;
input[15:0] dout_2;
input en_2;
output en_3;
output[15:0] dout_3;

reg[15:0] dout_3;
reg en_3;
parameter num="16"'h00ff;

always@(posedge clk)
begin
if(!rst) begin dout_3 <= 16'h0000;en_3 <= 0; end
else if(en_2) begin dout_3 <= dout_2-num;en_3 <= 1; end
else en_3 <= 0;
end

endmodule


module liu_4(clk,rst,dout_3,en_3,en_out,dout);
input clk;
input rst;
input[15:0] dout_3;
input en_3;
output en_out;
output[7:0] dout;

reg[7:0] dout;
reg en_out;

always@(posedge clk)
begin
if(!rst) begin dout <= 8'h00;en_out <= 0; end
else if(en_3) begin dout <= dout_3[7:0];en_out <= 1; end
else en_out <= 0;
end

endmodule