基于Verilog的高效率SPI模块,全静态,仅用15个宏 always, write, 网上

yuyang911220

网上那篇冗长的SPI代码实在不能忍了,自己写了一个,全静态,省却两个SPI里本来不应该有的CLR和CLK线,仅消耗15个宏单元,已经在EPM570上验证通过.

module spitest_v10(ledout,sdi,sdo,sck,rw,cs);
output reg[7:0] ledout;
input rw;  //Slaver read(0) & S write(1)
input sdi;  // spi data input
output reg sdo; // spi data output
input sck;  // spi clk
input cs;  // spi enable
reg[7:0] spi_out;
reg[7:0] spi_in;
reg msg_spiout_trg;
reg msg_spiout_fb;

[email=always@(posedge]always@(posedge[/email] sck)
begin
  if((cs==0)&(rw==0)) //MOSI enable
  begin
   spi_in[0:0]=sdi;
   spi_in=spi_in<<1;
  end
end
[email=always@(negedge]always@(negedge[/email] sck)
begin
  if(msg_spiout_trg)
   begin
    spi_out=8'h01;   //TXD assignment.U can put a variable instead of it.
    msg_spiout_fb=1;
   end
  else msg_spiout_fb=0;
  if((cs==0)&(rw==1)) //MISO enable
  begin
   sdo=spi_out[7:7];
   spi_out=spi_out<<1;
  end
end
[email=always@(posedge]always@(posedge[/email] cs)   //cs=1 means Master write complete
begin
  ledout=~spi_in;  //use data received,for example...
end
[email=always@(negedge]always@(negedge[/email] rw or posedge msg_spiout_fb) //Message of SPI MISO BUFF
begin
  if(rw==0)
   msg_spiout_trg=1;
  
  if(msg_spiout_fb==1)
   msg_spiout_trg=0;
end

endmodule