module jiakuankongzhi (reset,add_1,sub_1,cnt2);
input reset;
input sub_1;
input add_1;
output cnt2;
reg[4:0] cnt2;
always@(negedge reset or negedge add_1 or negedge sub_1)
begin
if(!reset)
cnt2<=5'b00000;
else if (!add_1)
begin
if (cnt2==5'b10100)
cnt2<=5'b00000;
else cnt2<=cnt2+1;
end
else if (!sub_1)
begin
if (cnt2==5'b00000)
cnt2<=5'b10100;
else cnt2<=cnt2-1;
end
end
endmodule 程序在QUARTUE仿真时报错! 哪位大侠帮忙解答下 | 
