标签: Signal

	版块	作者	回复/查看	最后发表
[下载]经典FPGA算法教材Digital Signal Processing with Field Programmable Gate ... 1 2 3 4 5 6 .. 10	FPGA/CPLD可编程逻辑	xiongguisheng 2005-12-6	140 / 45386	coolluoyi 2011-1-7 12:16
LSI Analog/Mixed Signal Opportunity	模拟电路	LSI_Tracey 2010-4-21	0 / 1338	LSI_Tracey 2010-4-21 18:09
real-time signal processing(基于c55x的实现，应用和实验)的ccs、matlab、c语言例	DSP技术	encaon 2005-11-2	2 / 1790	melancholp 2009-6-18 21:06
[求助]Signal tap 一个小问题		b01010101 2008-11-22	1 / 1932	b01010101 2008-11-23 20:18
[求助]那位仁兄有signal tap II 的破解方法		dongsheng029134 2008-7-6	1 / 1646	caopengly 2008-7-6 15:01
The signal * is incomplete,The signal dose not drive any load pins in the des		lamsam 2008-4-24	0 / 1051	lamsam 2008-4-24 13:33
signal tap 使用的问题	FPGA/CPLD可编程逻辑	xialixiong 2008-3-7	2 / 1211	caopengly 2008-3-7 14:02
安捷伦推出3GPP LTE信号生成软件Signal Studio		juliguo 2007-8-13	0 / 1021	juliguo 2007-8-13 11:22
(capature_signal)文件下载	FPGA/CPLD可编程逻辑	diypcb 2007-8-2	1 / 879	tinali 2007-8-7 19:13
[求助]在ISE中如何将FPGA的特定信号（内部signal）综合为不使用全局时钟资源？	FPGA/CPLD可编程逻辑	joy2008 2006-3-25	5 / 2158	stone133 2006-3-25 20:56
【滤波器】Digital Signal Processing--Filtering App	DSP技术	maeleton1 2005-12-15	7 / 1348	jiehv 2006-3-7 15:31
[求助]vhdl的中间signal信号可以提前定义成高阻吗？	FPGA/CPLD可编程逻辑	anny1209 2006-2-21	0 / 1031	anny1209 2006-2-21 16:12
MapLib:93 - Illegal LOC on symbol "clk" (pad signal=clk) or BUFGP		alywen 2006-1-19	1 / 2204	skyeasing 2006-1-19 16:32
DSP(Digital Signal Process)芯片的特点n	DSP技术	maeleton1 2005-10-28	0 / 963	maeleton1 2005-10-28 13:13
求教：编译时报“unresolved signal is multiply driven	FPGA/CPLD可编程逻辑	hp_2000 2005-9-29	0 / 1437	hp_2000 2005-9-29 15:20
急求英文版电子书Sensors and Signal Conditioning	资料共享	xz830906 2005-4-27	0 / 1142	xz830906 2005-4-27 22:01
“Putting Analog on the Bus”是否意指对Analog Signal进行A/D转换？	综合技术交流	ljp 2003-8-8	1 / 1053	samire 2003-8-8 14:15