|
 
- UID
- 72852
- 性别
- 男
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| 呵呵，今天从新回来，为了庆祝给你们发一个任意整数分频的代码：
module FREQ_DIVIDER(
clkin,
clr,
odd_even,
clk_even,
clk_odd,
clk_out
);
parameter N = 5;
input clkin;
input clr;
input odd_even; //when odd frequency devided, set to '1', otherwise, set to '0'
output clk_odd; //clock output after odd divided
output clk_even; //clock output after even divided
output clk_out;
reg out1;
reg out2;
reg [N/2:0] count1;
reg [N/2:0] count2;
reg clk_out;
wire clk_even;
wire clk_odd;
//wire odd_even = N - (N/2)*2;// this can be simulated , but can't be synthesible.
always @(posedge clkin or posedge clr )
begin
if ( clr == 1'b1 )
begin
count1 <= 0;
out1 <= 0;
end
else
begin
count1 <= count1 + 1;
if ( count1 == (N+1)/2-1 )
out1 <= ! out1;
else if ( count1== N-1 )
begin
out1 <= ~ out1;
count1 <= 0;
end
else;
end
end
always @( negedge clkin or posedge clr )
begin
if ( clr == 1'b1 )
begin
count2 <= 0;
out2 <= 0;
end
else
begin
count2 <= count2 + 1;
if ( count2 == (N+1)/2-1 )
out2 <= ! out2;
else if ( count2 == N-1 )
begin
out2 <= ~ out2;
count2 <= 0;
end
else;
end
end
assign clk_even = out1;
assign clk_odd = out1 | out2;//the constraints of the OR gate must be strict, otherwise,
//the 1:1 occupancy ratio can't be satisfied
always @( odd_even or clk_even or clk_odd )
begin
case ( odd_even )
0: clk_out = clk_even;
1: clk_out = clk_odd;
default: clk_out = clk_even;
endcase
end
endmodule |
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