程序和仿真结果：
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:18:25 05/08/06
-- Design Name:
-- Module Name: latch - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity vhdl1 is
port (
cerin:in std_logic;
cerout ut std_logic;
csin:in std_logic;
csoutut std_logic;
semrin:in std_logic;
semroutut std_logic;
ale: in std_logic ;
data_in : in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
da12_8: out std_logic_vector(4 downto 0)
);
end vhdl1;
architecture a of vhdl1 is
signal data_temp : std_logic_vector(7 downto 0);
begin
csout<=csin;
cerout<=cerin;
semrout<=semrin;
data_out<=data_temp;
da12_8<="ZZZZZ";
process (ale,cerin,data_in)
begin
if (cerin='0') then
if (ale='1') then
data_temp<=data_in;
end if;
else
data_temp<="ZZZZZZZZ";
end if;
end process;
end a ;
|
