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FPGA Configuration Overview
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Once your hardware platform design is complete, you can generate an FPGA configuration bitstream. If your embedded system is a submodule in a top-level ISE design, use Project Navigator to generate the bitstream containing all your embedded hardware platform and any non-processor custom logic. If you are using XPS stand-alone (without Project Navigator), you can run the Generate Bitstream command in XPS, as described in Implementing the Hardware Platform. At this point, you have only a "hardware bitstream", and you are not ready to apply it to an FPGA until you accommodate the software component of your embedded system.
Once your embedded software development is complete, you can choose one of three ways to run it on the hardware:
If your application executable resides in on-chip memory regions, you can merge the executable ELF file into the hardware bitstream so that it gets loaded into on-chip memory, ready to execute, every time the FPGA is configured.
During prototyping, XPS can dynamically download your executable to the board via the JTAG cable connected to the FPGA. In this case, you select a bootloop to be merged into the bitstream to initialize on-chip memory so that the processor remains in a static state until software downloading can be completed.
For production systems, you can store executables residing in off-chip memory regions in a non-volatile memory device, such as flash PROM or along with the configuration bitstream in a SystemACE device. In this case, you would configure a bootloader executable to be merged into the hardware bitstream to initialize on-chip memory. Then each time the FPGA is configured or reset, the bootloader copies the application executable to a suitable (volatile) memory device and starts it running.
You must select the desired initialization executable (your on-chip application, bootloop or bootloader) in XPS for each processor in your embedded platform. You are then ready to perform the "update bitstream" step, which merges your selected executable into the hardware bitstream. The result is the "download bitstream," which is ready to be applied to the FPGA. You can perform the "update bitstream" step in either Project Navigator or XPS (stand-alone).
For prototyping, you connect an appropriate download cable between your host computer and the JTAG port of the FPGA device on your development board. You can then dynamically download your bitstream to the FPGA using either Project Navigator or XPS (stand-alone mode). When finished, the embedded processors in your FPGA begin executing your software program.
For production, you typically store your "download bitstream" into an off-chip non-volatile memory device, such as SystemACE or serial PROM, from which the FPGA is configured every time the board is powered on or reset. When configuration completes, the embedded processors in your FPGA begin executing your software program. | 
