一般来说,书上只有思路是对的,它提供的例子十有八九是不能直接使用的,多多少少要做一些修改,他这个例子错的有点多了; 改成下面那样就能实现8分频了,还有很多种写法都可以实现,有时间你可以试试看。 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity clk_8d is port(clk:in std_logic; rst:in std_logic; clk_dut std_logic); end clk_8d; architecture one of clk_8d is signal count:std_logic_vector(1 downto 0); signal clk_d_temp:std_logic; begin process(rst,clk) begin if(rst='0')then clk_d <= '0'; count(1 downto 0)<="00"; else if (clk'event and clk='1')then count(1 downto 0)<=count(1 downto 0)+"01"; if(count(1 downto 0) = "11")then clk_d_temp <= not clk_d_temp; else null; end if; end if; clk_d<=clk_d_temp; end if; end process; end one;
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