我用ep1c12q240做ad0809的ad转换 仿真能实现我的功能 但是一配置到硬件fpga没有输出，状态机也不工作，问题出在哪里？fpga和ad的时钟都检测正常 状态机程序 library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adc0809 is port(
clk : in std_logic;
eoc : in std_logic;
D : in std_logic_vector(7 downto 0);
lock : out std_logic;
ale : out std_logic;
start : out std_logic;
oe : out std_logic;
addr : out std_logic_vector(2 downto 0):="000";
data : out std_logic_vector(7 downto 0)
); end entity; architecture func of adc0809 is -- Build an enumerated type for the state machine
type state_type is (st0, st1, st2, st3, st4, st5, st6);
signal current_state,next_state : state_type:=st0;
signal lock1 : std_logic;
signal reg : std_logic_vector(7 downto 0);
begin
-- Logic to advance to the next state
process (current_state, eoc)
begin
case current_state is
when st0=>
ale<='0';
start<='0';
oe<='0';
lock<='0';
lock1<='0';
next_state<=st1;
when st1=>
ale<='1';
start<='0';
oe<='0';
lock<='0';
lock1<='0';
next_state<=st2;
when st2=>
ale<='0';
start<='1';
oe<='0';
lock<='0';
lock1<='0';
next_state<=st3;
when st3=>
ale<='0';
start<='0';
oe<='0';
lock<='0';
lock1<='0';
if(eoc='0')then
next_state<=st4;
else
next_state<=st3;
end if;
when st4=>
ale<='0';
start<='0';
oe<='0';
lock<='0';
lock1<='0';
if(eoc='1')then
next_state<=st5;
else
next_state<=st4;
end if;
when st5=>
ale<='0';
start<='0';
oe<='1';
lock<='0';
lock1<='0';
next_state<=st6;
when st6=>
ale<='0';
start<='0';
oe<='1';
lock<='1';
lock1<='1';
next_state<=st0;
when others=>
next_state<=st0;
end case;
end process;
process (clk)
begin
if (clk'event and clk='1') then
current_state<=next_state;
end if;
end process;
-- Output depends solely on the current state
process (lock1)
begin
if (lock1='1' and lock1'event) then
reg<=D;
end if;
end process;
data<=reg;
end func;
[此贴子已经被作者于2008-4-2 13:29:25编辑过] | 
