大家帮帮我，谢谢！ color, error, online

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Design dff has been optimized and fit into device XC95108-7-PC84.
ERROR:Cpld:1244 - Unexpected Exceptions
FATAL_ERROR:Cpldortability/export/Port_Main.h:127:1.126.30.1 - This
   application has discovered an exceptional condition from which it cannot
   recover.  Process will terminate.  To resolve this error, please consult the
   Answers Database and other online resources at http://support.xilinx.com. If
   you need further assistance, please open a Webcase by clicking on the
   "WebCase" link at http://support.xilinx.com
ERROR: Fit failed
Reason:
Process "Fit" did not complete.

这到底是什么原因啊？我一直出现这个问题？头疼死了。布置如何是好啊？

我心善良

换一个芯片试试 看看能不能下进去

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我是用VHDL编的一个计数的程序，调试的时候，XST这一关过了，但是到implement时，只要一出错，就是这个错误，提示又不明确，真是头痛死了。

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我还做过几个测试，把本来implement过关的程序故意弄错，出现上面这个错误后，再按原来的正确的改回来，出错依旧。让人感觉就是程序一出现上面那个错，就“活”不过来了。唉，真是没办法啊 。我是新手，遇到这样的问题，真实。。。

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我试着换过芯片啊，还是一样的。望各位指点指点啊！谢谢拉！

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不是啊，我已经重装过了 。真不知道是什么问题啊 ？？？请各位不吝赐教！！！

stone133

程序发上来吧

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entity fp is
Port ( clk1 : in std_logic;
reset : in std_logic;
clk2 : in std_logic;
output1 : out std_logic;
output2ut std_logic);

end fp;

architecture Behavioral of fp is
component Div
Port ( clk : in std_logic;
reset : in std_logic;
clko : out std_logic);
end component;
component DFF
Port ( D : in std_logic;
reset : in std_logic;
clk : in std_logic;
Q : out std_logic);
end component;

signal clko:std_logic;
begin
output1<=clko;
A1iv
port map(clk1,reset,clko);
A2FF
port map(clko,reset,clk2,output2);

end Behavioral;

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各位,不好意思,上面的确程序发成这样啊,不过,还是真诚的请大家看看啊,是个很简单的程序啊,分频,然后输出分频,就这个功能啊.另外两component的程序，我下面就发啊．请各位大吓帮帮我，到底是什么原因啊，我在次先谢谢各位拉：）

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entity Div is
Port ( clk : in std_logic;
reset : in std_logic;
clko: out std_logic);
end Div;


architecture Behavioral of Div is
signal cou:std_logic_vector(3 downto 0):="0000";

begin
process
begin
wait until clk='1';
if reset='1' then
cou<="0000";
else
cou<=cou+1;
end if;
end process;
clko<=not cou(3);
end Behavioral;

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entity Dff is
Port ( D : in std_logic;
clk : in std_logic;
reset : in std_logic;
Q : out std_logic);
end Dff;

architecture Behavioral of Dff is
begin
process(clk,D,reset)
begin
if reset='1' then
Q<='0';
elsif clk'event and clk='1' then
Q<=D;
end if;
end process;
end Behavioral;

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我在把第一个程序发一遍啊，

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entity fp is
Port ( clk1 : in std_logic;
reset : in std_logic;
clk2 : in std_logic;
output1 : out std_logic;
output2ut std_logic);

end fp;

architecture Behavioral of fp is
component Div
Port ( clk : in std_logic;
reset : in std_logic;
clko : out std_logic);
end component;
component DFF
Port ( D : in std_logic;
reset : in std_logic;
clk : in std_logic;
Q : out std_logic);
end component;

signal clko:std_logic;
begin
output1<=clko;
A1iv
port map(clk1,reset,clko);
A2FF
port map(clko,reset,clk2,output2);

end Behavioral;

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大家好，怎么没人吭声呢？是不被我的上面那一段程序给吓跑了呢？：）其实程序很简单的，只是把它拈上来就成这样了，实在抱歉啊

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entity fp is
Port ( clk1 : in std_logic;
reset : in std_logic;
clk2 : in std_logic;
output1 : out std_logic;
output2ut std_logic);

end fp;

architecture Behavioral of fp is
component Div
Port ( clk : in std_logic;
reset : in std_logic;
clko : out std_logic);
end component;
component DFF
Port ( D : in std_logic;
reset : in std_logic;
clk : in std_logic;
Q : out std_logic);
end component;

signal clko:std_logic;

begin
output1<=clko;
A1iv
port map(clk1,reset,clko);
A2FF
port map(clko,reset,clk2,output2);

end Behavioral;