我试的小代码，在ise8.2中跑的 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all; entity XOR2 is
PORT( A,B : IN STD_LOGIC;
Y : OUT STD_LOGIC);
end XOR2; architecture Behavioral of XOR2 is
SIGNAL COMB : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
 ROCESS(A,B)
BEGIN
COMB<=A&B;
CASE COMB IS
WHEN "00" => Y<='0';
WHEN "01" => Y<='1';
WHEN "10" => Y<='1';
WHEN "11" => Y<='0';
WHEN OTHERS => Y<='X';
END CASE;
END PROCESS;
end Behavioral; 综合没问题，可是在仿真时，输出恒为低，没实现异或功能。另外，只要在进程中用到变量和信号，就出现这种情况 求教 | 
