library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity n_div is
port(n:in std_logic_vector(7 downto 0);
clk:in std_logic;
clkoutut std_logic);
end n_div;
architecture rtl of n_div is
signal cnt:std_logic_vector(7 downto 0);
signal n_t,n_1:std_logic_vector(7 downto 0);
begin
n_1<=n-1;
n_t<='0' & n(7 downto 1);
process(n,clk)
begin
if clk'event and clk='1' then
if cnt=n_1 then
cnt<="00000000";
else
cnt<=cnt+1;
end if;
if cnt
clkout<='0'
else
clkout<='1';
end if;
end if;
end process;
end rtl;
ut std_logic);