Frequency-Synthesis Output Clock - CLKFX
The CLKFX output clock provides a clock with the following frequency definition:
CLKFX frequency = (M/D) × effective CLKIN frequency
In this equation, M is the multiplier (numerator) with a value defined by the
CLKFX_MULTIPLY attribute. D is the divisor (denominator) with a value defined by the
CLKFX_DIVIDE attribute. Specifications for M and D, as well as input and output
frequency ranges for the frequency synthesizer, are provided in the Virtex-4 Data Sheet.
The rising edge of CLKFX output is phase aligned to the rising edges of CLK0, CLK2X, and
CLKDV. When M and D to have no common factor, the alignment occurs only once every
D cycles of CLK0.[em06]
BUFGCTRL – Internal Global Clock Buffer
Any BUFGCTRL can drive any DCM in the Virtex-4 device using dedicated global
routing. A BUFGCTRL can drive the DCM CLKIN pin when used to connect two
DCMs in series.
我也没有这样用过，不过你看这段话对你有帮助没？第一个DCM的输出是不是不满足第二个DCM输入的条件？
