LIBRARY IEEE;ffice ffice" />
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
ENTITY MY IS
PORT(
a,f1,f2:IN STD_LOGIC;
y:OUT STD_LOGIC);
END MY;
ARCHITECTURE Behave OF MY IS
BEGIN
BLK:BLOCK
VARIABLE tmp1,tmp2,tmp3:STD_LOGIC;
BEGIN
tmp1:=(not a) and f1;
tmp2:=a and f2;
tmp3:=tmp1 or tmp2;
y<=tmp3;
END BLOCK BLK;
END Behave;
为啥老出现下面的错误：
ERROR INE 13:VHDL syntax error:found illegal use of a variable declaration in block declarative part
高手大大们指点一下！ 谢谢了 | 
