[求助]： 求助

lgj680125

利用cpld设计：40M的输入时钟，cpu可以动态设置的分频倍数，实现可变得分频输出。我在设计中能实现固定分频，可控分频未能实现，希望用经验的大虾指点。 

stone133

如果用计数器分频，把计数的数值做成可选的，这个选择由cpu控制信号来完成

lgj680125

请教：节选相关部分如下：
问题是：编译无法通过。提示：Mapping a total of 103 equations into 8 function blocks........................................................ERROR:Cpld:892 - Cannot place signal count_16<0>. Consider reducing the
collapsing input limit or the product term limit to prevent the fitter from
creating high input and/or high product term functions.
See the fitter report for details.
ERROR:Cpld:868 - Cannot fit the design into any of the specified devices with
the selected implementation options.
ERROR: Fit failed
Reason:
Process "Fit" did not complete.
如果process1中去掉reghz <= databus(15 downto 0);动态设置reghz值，实现固定分频，成功。如果process1不动，而process2中if( count_16 = reghz )THEN 改为if( count_16 = 12500 )THEN 与固定值比较编译也能通过。

process ( rst,we,enhz ) --复位信号，写信号，cpu控制频率的片选信号
begin
if ( rst = RST_ACTIVE ) then
reghz <= X"30d4"; －－－－－－－－－－复位赋初值
elsif ( we 'event and we = HIGH_ACTIVE ) then
if( enhz = LOW_ACTIVE ) then
reghz <= databus(15 downto 0);－－－－动态改变分频值
end if;
end if;
end process;

process(clk)－－－－－40M晶振时钟count_16为16位计数器，st_ad为分频输出信号
begin
if( clk'EVENT AND clk='1' )THEN
if( count_16 = reghz )THEN
count_16 <= X"0000" ;
else
count_16 <= count_16+'1';
end if;

if( count_16 < 6250 )then
st_ad <= '1';
else
st_ad <= '0';
end if;
end if ;
end process;