module uart(clk,rst,tx_data,tx_data_valid,tx_data_ack,txd);
input clk;
input rst;
input [7:0]tx_data;
input tx_data_valid;
output reg tx_data_ack;
output reg txd;
parameter baud=10;
reg[10:0] tx_shift;
reg ready;
reg tick_cnt;
reg tick_now;
always@(posedge clk )
begin
if(rst)
begin
tick_cnt<=0;
tick_now<=1'b0;
end
else if(tick_cnt==(baud-1))
begin
tick_cnt<=0;
tick_now<=1'b1;
end
else
begin
tick_now<=1'b0;
tick_cnt<=tick_cnt+1;
end
end
end
always@(posedge clk )
begin
if(rst)
begin
tx_shift<={11'b00000000001};
ready<=1'b1;
end
else
begin
if(!ready&tick_now)
begin
tx_shift<={1'b0,tx_shift[10:1]};
tx_data_ack<=1'b0;
ready<=~|tx_shift[10:1];
end
else if(ready&tx_data_valid)
begin
tx_shift<={1'b1,tx_data,1'b0};
tx_data_ack<=1'b1;
ready<=1'b0;
end
else
begin
tx_data_ack<=1'b0;
ready<=~|tx_shift[10:1];
end
end
end
assign txd=tx_shift[0];
end
endmodule |
