Error: Can't synthesize current design -- design does not contain any logic 这个错误是怎么回事？ 先谢了！！！ 源程序： `include "adder4.v" `timescale 1ns/1ns module adder_tp;
reg[3:0] a,b;
reg cin;
wire[3:0] sum;
wire cout;
integer i,j; adder4 myadder(cout,sum,a,b,cin);
always #5 cin=~cin;
initial
begin
a=0;b=0;cin=0;
for(i=1;i<16;i=i+1)
#10 a=i;
end
initial
begin
for(j=1;j<16;j=j+1)
#10 b=j;
end initial
begin
$monitor($time,,,"%d + %d + %b={%b,%d}",a,b,cin,cout,sum);
#160 $finish;
end
endmodule
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