下面逻辑呢？
module dff_sys(I_clock, I_data, O_data);
input I_clock, I_data;
output O_data;
reg R_b, R_c, R_d;
assign O_data = R_d;
always @(posedge I_clock)
begin
R_b = I_data;
R_c = R_b;
R_d <= R_c;
end
endmodule
module dff_sys(I_clock, I_data, O_data);
input I_clock, I_data;
output O_data;
reg R_b, R_c, R_d;
assign O_data = R_d;
always @(posedge I_clock)
begin
R_b <= I_data;
R_c <= R_b;
R_d <= R_c;
end
endmodule |
