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FPGA/CPLD可编程逻辑

[ 26527 主题 / 25683 回复 ]

版块介绍: 讨论关于FPGA和CPLD的相关话题!

版主: boyfly, stone133, flanix, bydxdtcdj, 电子狂热, xcx_hust, benbenfei, AndyLee008

FPGA/CPLD可编程逻辑

    标题 作者 回复/查看 最后发表
common   FPGA基础知识2(Xilinx Altera FPGA中的逻辑资源 --Slices VS LE比较) look_w 2017-11-4 0/421 look_w 2017-11-4 13:00
common   FPGA基础知识1(FPGA芯片结构) look_w 2017-11-4 0/632 look_w 2017-11-4 12:58
common   FPGA基础知识0(查找表LUT和编程方式) look_w 2017-11-4 0/401 look_w 2017-11-4 12:57
common   XILINX编译软件ISE怎样在ChipScope 加入被优化掉的信号 look_w 2017-11-4 0/602 look_w 2017-11-4 12:56
common   XILINX DDR3 wr_count rd_count不能连续计数问题 look_w 2017-11-4 0/359 look_w 2017-11-4 12:55
common   FPGA设计者的5项基本功 look_w 2017-10-20 0/342 look_w 2017-10-20 21:47
common   开发经验分享 look_w 2017-10-20 0/374 look_w 2017-10-20 21:47
common   基于NIOS-II的示波器:PART4 系统调试&测试(1)) look_w 2017-10-20 0/399 look_w 2017-10-20 21:45
common   不同的AXI总线卷积加速模块7 look_w 2017-10-20 0/654 look_w 2017-10-20 21:42
common   不同的AXI总线卷积加速模块6 look_w 2017-10-20 0/573 look_w 2017-10-20 21:42
common   不同的AXI总线卷积加速模块5 look_w 2017-10-20 0/629 look_w 2017-10-20 21:41
common   不同的AXI总线卷积加速模块4 look_w 2017-10-20 0/492 look_w 2017-10-20 21:40
common   不同的AXI总线卷积加速模块3 look_w 2017-10-20 0/369 look_w 2017-10-20 21:39
common   不同的AXI总线卷积加速模块2 look_w 2017-10-20 0/645 look_w 2017-10-20 21:38
common   不同的AXI总线卷积加速模块 look_w 2017-10-20 0/412 look_w 2017-10-20 21:38
common   FPGA无损压缩实现 look_w 2017-10-20 0/410 look_w 2017-10-20 21:34
common   时序约束 look_w 2017-10-20 0/693 look_w 2017-10-20 21:33
common   在FPGA中实现源同步LVDS接收字对齐 look_w 2017-10-20 0/399 look_w 2017-10-20 21:31
common   如何提高电路工作频率 look_w 2017-10-20 0/761 look_w 2017-10-20 21:28
common   FPGA经验介绍 look_w 2017-10-20 0/387 look_w 2017-10-20 21:27
common   Xilinx Virtex6 GTX Transceiver设计总结 look_w 2017-10-20 0/385 look_w 2017-10-20 21:26
common   Xilinx FPGA的SelectMAP与BPI配置模式的比较 look_w 2017-10-20 0/389 look_w 2017-10-20 21:24
common   问题: DxDesigner中的十字光标缺省为小十字,想转换为十字光标。 look_w 2017-10-20 0/504 look_w 2017-10-20 21:23
common   ISE中下载Xilinx的bit文件失败时的处理方案 look_w 2017-10-20 0/752 look_w 2017-10-20 21:22
common   FPGA低温无法启动解决 look_w 2017-10-20 0/562 look_w 2017-10-20 21:21
common   timescale使用 look_w 2017-10-20 0/627 look_w 2017-10-20 21:18
common   ILA VIO 使用 look_w 2017-10-20 0/433 look_w 2017-10-20 21:17
common   ILA IP内核 look_w 2017-10-20 0/761 look_w 2017-10-20 21:16
common   定点数与浮点数表示 look_w 2017-10-20 0/579 look_w 2017-10-20 21:15
common   Verilog 运算符 look_w 2017-10-20 0/603 look_w 2017-10-20 21:14
common   FIFO读写控制 look_w 2017-10-20 0/816 look_w 2017-10-20 21:14
common   PAM延时输出 look_w 2017-10-20 0/376 look_w 2017-10-20 21:13
common   上线调试 下线调试 look_w 2017-10-20 0/569 look_w 2017-10-20 21:12
common   FPGA常用写法 look_w 2017-10-20 0/770 look_w 2017-10-20 21:11
common   在ISE中使用CORDIC核时应该注意 look_w 2017-10-20 0/563 look_w 2017-10-20 21:10
common   FPGA全局时钟处理 look_w 2017-10-20 0/388 look_w 2017-10-20 21:10
common   inout端口使用方法 look_w 2017-10-20 0/372 look_w 2017-10-20 21:09
common   FPGA时序分析 look_w 2017-10-20 0/827 look_w 2017-10-20 21:07
common   FPGA跑飞 look_w 2017-10-20 0/325 look_w 2017-10-20 21:06
common   FPGA时钟 look_w 2017-10-20 0/600 look_w 2017-10-20 21:05
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